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# perfmon_pebs_core_smpl.h

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    00001 /*
    00002  * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P.
    00003  *               Contributed by Stephane Eranian <eranian@hpl.hp.com>
    00004  *
    00005  * This file implements the sampling format to support Intel
    00006  * Precise Event Based Sampling (PEBS) feature of Intel
    00007  * Core and Atom processors.
    00008  *
    00009  * What is PEBS?
    00010  * ------------
    00011  *  This is a hardware feature to enhance sampling by providing
    00012  *  better precision as to where a sample is taken. This avoids the
    00013  *  typical skew in the instruction one can observe with any
    00014  *  interrupt-based sampling technique.
    00015  *
    00016  *  PEBS also lowers sampling overhead significantly by having the
    00017  *  processor store samples instead of the OS. PMU interrupt are only
    00018  *  generated after multiple samples are written.
    00019  *
    00020  *  Another benefit of PEBS is that samples can be captured inside
    00021  *  critical sections where interrupts are masked.
    00022  *
    00023  * How does it work?
    00024  *  PEBS effectively implements a Hw buffer. The Os must pass a region
    00025  *  of memory where samples are to be stored. The region can have any
    00026  *  size. The OS must also specify the sampling period to reload. The PMU
    00027  *  will interrupt when it reaches the end of the buffer or a specified
    00028  *  threshold location inside the memory region.
    00029  *
    00030  *  The description of the buffer is stored in the Data Save Area (DS).
    00031  *  The samples are stored sequentially in the buffer. The format of the
    00032  *  buffer is fixed and specified in the PEBS documentation.  The sample
    00033  *  format does not change between 32-bit and 64-bit modes unlike on the
    00034  *  Pentium 4 version of PEBS.
    00035  *
    00036  *  What does the format do?
    00037  *   It provides access to the PEBS feature for both 32-bit and 64-bit
    00038  *   processors that support it.
    00039  *
    00040  *   The same code and data structures are used for both 32-bit and 64-bi
    00041  *   modes. A single format name is used for both modes. In 32-bit mode,
    00042  *   some of the extended registers are written to zero in each sample.
    00043  *
    00044  *   It is important to realize that the format provides a zero-copy
    00045  *   environment for the samples, i.e,, the OS never touches the
    00046  *   samples. Whatever the processor write is directly accessible to
    00047  *   the user.
    00048  *
    00049  *   Parameters to the buffer can be passed via pfm_create_context() in
    00050  *   the pfm_pebs_smpl_arg structure.
    00051  */
    00052 #ifndef __PERFMON_PEBS_CORE_SMPL_H__
    00053 #define __PERFMON_PEBS_CORE_SMPL_H__ 1
    00054
    00055 #ifdef __cplusplus
    00056 extern "C" {
    00057 #endif
    00058
    00059 #include <perfmon/perfmon.h>
    00060
    00061 #define PFM_PEBS_CORE_SMPL_NAME "pebs_core"
    00062
    00063 /*
    00064  * format specific parameters (passed at context creation)
    00065  */
    00066 typedef struct {
    00067         uint64_t        cnt_reset;      /* counter reset value */
    00068         uint64_t        buf_size;       /* size of the buffer in bytes */
    00069         uint64_t        intr_thres;     /* index of interrupt threshold entry */
    00070         uint64_t        reserved[6];    /* for future use */
    00071 } pfm_pebs_core_smpl_arg_t;
    00072
    00073 /*
    00074  * DS Save Area
    00075  */
    00076 typedef struct {
    00077         uint64_t        bts_buf_base;
    00078         uint64_t        bts_index;
    00079         uint64_t        bts_abs_max;
    00080         uint64_t        bts_intr_thres;
    00081         uint64_t        pebs_buf_base;
    00082         uint64_t        pebs_index;
    00083         uint64_t        pebs_abs_max;
    00084         uint64_t        pebs_intr_thres;
    00085         uint64_t        pebs_cnt_reset;
    00086 } pfm_ds_area_core_t;
    00087
    00088 /*
    00089  * This header is at the beginning of the sampling buffer returned to the user.
    00090  *
    00091  * Because of PEBS alignement constraints, the actual PEBS buffer area does
    00092  * not necessarily begin right after the header. The hdr_start_offs must be
    00093  * used to compute the first byte of the buffer. The offset is defined as
    00094  * the number of bytes between the end of the header and the beginning of
    00095  * the buffer. As such the formula is:
    00096  *      actual_buffer = (unsigned long)(hdr+1)+hdr->hdr_start_offs
    00097  */
    00098 typedef struct {
    00099         uint64_t                overflows;      /* #overflows for buffer */
    00100         size_t                  buf_size;       /* bytes in the buffer */
    00101         size_t                  start_offs;     /* actual buffer start offset */
    00102         uint32_t                version;        /* smpl format version */
    00103         uint32_t                reserved1;      /* for future use */
    00104         uint64_t                reserved2[5];   /* for future use */
    00105         pfm_ds_area_core_t      ds;             /* DS management Area */
    00106 } pfm_pebs_core_smpl_hdr_t;
    00107
    00108 /*
    00109  * PEBS record format as for both 32-bit and 64-bit modes
    00110  */
    00111 typedef struct {
    00112         uint64_t eflags;
    00113         uint64_t ip;
    00114         uint64_t eax;
    00115         uint64_t ebx;
    00116         uint64_t ecx;
    00117         uint64_t edx;
    00118         uint64_t esi;
    00119         uint64_t edi;
    00120         uint64_t ebp;
    00121         uint64_t esp;
    00122         uint64_t r8;    /* 0 in 32-bit mode */
    00123         uint64_t r9;    /* 0 in 32-bit mode */
    00124         uint64_t r10;   /* 0 in 32-bit mode */
    00125         uint64_t r11;   /* 0 in 32-bit mode */
    00126         uint64_t r12;   /* 0 in 32-bit mode */
    00127         uint64_t r13;   /* 0 in 32-bit mode */
    00128         uint64_t r14;   /* 0 in 32-bit mode */
    00129         uint64_t r15;   /* 0 in 32-bit mode */
    00130 } pfm_pebs_core_smpl_entry_t;
    00131
    00132 #define PFM_PEBS_CORE_SMPL_VERSION_MAJ 1U
    00133 #define PFM_PEBS_CORE_SMPL_VERSION_MIN 0U
    00134 #define PFM_PEBS_CORE_SMPL_VERSION (((PFM_PEBS_CORE_SMPL_VERSION_MAJ&0xffff)<<16)|\
    00135                                    (PFM_PEBS_CORE_SMPL_VERSION_MIN & 0xffff))
    00136
    00137 #ifdef __cplusplus
    00138 };
    00139 #endif
    00140
    00141 #endif /* __PERFMON_PEBS_CORE_SMPL_H__ */

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