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# pfmlib_amd64.h

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    00001 /*
    00002  * AMD64 PMU specific types and definitions (64 and 32 bit modes)
    00003  *
    00004  * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P.
    00005  * Contributed by Stephane Eranian <eranian@hpl.hp.com>
    00006  *
    00007  * Permission is hereby granted, free of charge, to any person obtaining a copy
    00008  * of this software and associated documentation files (the "Software"), to deal
    00009  * in the Software without restriction, including without limitation the rights
    00010  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
    00011  * of the Software, and to permit persons to whom the Software is furnished to do so,
    00012  * subject to the following conditions:
    00013  *
    00014  * The above copyright notice and this permission notice shall be included in all
    00015  * copies or substantial portions of the Software.
    00016  *
    00017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
    00018  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
    00019  * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
    00020  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
    00021  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
    00022  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
    00023  */
    00024
    00025 #ifndef __PFMLIB_AMD64_H__
    00026 #define __PFMLIB_AMD64_H__
    00027
    00028 #include <stdint.h>
    00029
    00030 /*
    00031  * privilege level mask usage for AMD64:
    00032  *
    00033  * PFM_PLM0 = OS (kernel, hypervisor, ..)
    00034  * PFM_PLM1 = invalid parameters
    00035  * PFM_PLM2 = invalid parameters
    00036  * PFM_PLM3 = USR (user level)
    00037  */
    00038
    00039 #ifdef __cplusplus
    00040 extern "C" {
    00041 #endif
    00042
    00043 #define PMU_AMD64_MAX_COUNTERS  4       /* total numbers of performance counters */
    00044
    00045 /*
    00046  * AMD64 MSR definitions
    00047  */
    00048
    00049 typedef union {
    00050         uint64_t val;                           /* complete register value */
    00051         struct {
    00052                 uint64_t sel_event_mask:8;      /* event mask */
    00053                 uint64_t sel_unit_mask:8;       /* unit mask */
    00054                 uint64_t sel_usr:1;             /* user level */
    00055                 uint64_t sel_os:1;              /* system level */
    00056                 uint64_t sel_edge:1;            /* edge detec */
    00057                 uint64_t sel_pc:1;              /* pin control */
    00058                 uint64_t sel_int:1;             /* enable APIC intr */
    00059                 uint64_t sel_res1:1;            /* reserved */
    00060                 uint64_t sel_en:1;              /* enable */
    00061                 uint64_t sel_inv:1;             /* invert counter mask */
    00062                 uint64_t sel_cnt_mask:8;        /* counter mask */
    00063                 uint64_t sel_event_mask2:4;     /* 10h only: event mask [11:8] */
    00064                 uint64_t sel_res2:4;            /* reserved */
    00065                 uint64_t sel_guest:1;           /* 10h only: guest only counter */
    00066                 uint64_t sel_host:1;            /* 10h only: host only counter */
    00067                 uint64_t sel_res3:22;           /* reserved */
    00068         } perfsel;
    00069 } pfm_amd64_sel_reg_t; /* MSR 0xc001000-0xc001003 */
    00070
    00071 typedef union {
    00072         uint64_t val;                           /* complete register value */
    00073         struct {
    00074                 uint64_t ctr_count:48;          /* 48-bit hardware counter  */
    00075                 uint64_t ctr_res1:16;           /* reserved */
    00076         } perfctr;
    00077 } pfm_amd64_ctr_reg_t; /* MSR 0xc001004-0xc001007 */
    00078
    00079 typedef union {
    00080         uint64_t val;                           /* complete register value */
    00081         struct {
    00082                 uint64_t ibsfetchmaxcnt:16;
    00083                 uint64_t ibsfetchcnt:16;
    00084                 uint64_t ibsfetchlat:16;
    00085                 uint64_t ibsfetchen:1;
    00086                 uint64_t ibsfetchval:1;
    00087                 uint64_t ibsfetchcomp:1;
    00088                 uint64_t ibsicmiss:1;
    00089                 uint64_t ibsphyaddrvalid:1;
    00090                 uint64_t ibsl1tlbpgsz:2;
    00091                 uint64_t ibsl1tlbmiss:1;
    00092                 uint64_t ibsl2tlbmiss:1;
    00093                 uint64_t ibsranden:1;
    00094                 uint64_t reserved:6;
    00095         } reg;
    00096 } ibsfetchctl_t; /* MSR 0xc0011030 */
    00097
    00098 typedef union {
    00099         uint64_t val;                           /* complete register value */
    00100         struct {
    00101                 uint64_t ibsopmaxcnt:16;
    00102                 uint64_t reserved1:1;
    00103                 uint64_t ibsopen:1;
    00104                 uint64_t ibsopval:1;
    00105                 uint64_t ibsopcntl:1;
    00106                 uint64_t reserved2:44;
    00107         } reg;
    00108 } ibsopctl_t; /* MSR 0xc0011033 */
    00109
    00110 typedef union {
    00111         uint64_t val;                           /* complete register value */
    00112         struct {
    00113                 uint64_t ibscomptoretctr:16;
    00114                 uint64_t ibstagtoretctr:16;
    00115                 uint64_t ibsopbrnresync:1;
    00116                 uint64_t ibsopmispreturn:1;
    00117                 uint64_t ibsopreturn:1;
    00118                 uint64_t ibsopbrntaken:1;
    00119                 uint64_t ibsopbrnmisp:1;
    00120                 uint64_t ibsopbrnret:1;
    00121                 uint64_t reserved:26;
    00122         } reg;
    00123 } ibsopdata_t; /* MSR 0xc0011035 */
    00124
    00125 typedef union {
    00126         uint64_t val;                           /* complete register value */
    00127         struct {
    00128                 uint64_t nbibsreqsrc:3;
    00129                 uint64_t reserved1:1;
    00130                 uint64_t nbibsreqdstproc:1;
    00131                 uint64_t nbibsreqcachehitst:1;
    00132                 uint64_t reserved2:58;
    00133         } reg;
    00134 } ibsopdata2_t; /* MSR 0xc0011036 */
    00135
    00136 typedef union {
    00137         uint64_t val;                           /* complete register value */
    00138         struct {
    00139                 uint64_t ibsldop:1;
    00140                 uint64_t ibsstop:1;
    00141                 uint64_t ibsdcl1tlbmiss:1;
    00142                 uint64_t ibsdcl2tlbmiss:1;
    00143                 uint64_t ibsdcl1tlbhit2m:1;
    00144                 uint64_t ibsdcl1tlbhit1g:1;
    00145                 uint64_t ibsdcl2tlbhit2m:1;
    00146                 uint64_t ibsdcmiss:1;
    00147                 uint64_t ibsdcmissacc:1;
    00148                 uint64_t ibsdcldbnkcon:1;
    00149                 uint64_t ibsdcstbnkcon:1;
    00150                 uint64_t ibsdcsttoldfwd:1;
    00151                 uint64_t ibsdcsttoldcan:1;
    00152                 uint64_t ibsdcucmemacc:1;
    00153                 uint64_t ibsdcwcmemacc:1;
    00154                 uint64_t ibsdclockedop:1;
    00155                 uint64_t ibsdcmabhit:1;
    00156                 uint64_t ibsdclinaddrvalid:1;
    00157                 uint64_t ibsdcphyaddrvalid:1;
    00158                 uint64_t reserved1:13;
    00159                 uint64_t ibsdcmisslat:16;
    00160                 uint64_t reserved2:16;
    00161         } reg;
    00162 } ibsopdata3_t; /* MSR 0xc0011037 */
    00163
    00164 /*
    00165  * AMD64 specific input parameters for the library
    00166  */
    00167
    00168 typedef struct {
    00169         uint32_t        cnt_mask;       /* threshold ([4-255] are reserved) */
    00170         uint32_t        flags;          /* counter specific flag */
    00171 } pfmlib_amd64_counter_t;
    00172
    00173 #define PFM_AMD64_SEL_INV       0x1     /* inverse */
    00174 #define PFM_AMD64_SEL_EDGE      0x2     /* edge detect */
    00175 #define PFM_AMD64_SEL_GUEST     0x4     /* guest only */
    00176 #define PFM_AMD64_SEL_HOST      0x8     /* host only */
    00177
    00178 /*
    00179  * IBS input parameters
    00180  *
    00181  * Maxcnt specifies the maximum count value of the periodic counter,
    00182  * 20 bits, bits 3:0 are always set to zero.
    00183  */
    00184 typedef struct {
    00185         unsigned int maxcnt;
    00186         unsigned int options;
    00187 } ibs_param_t;
    00188
    00189 /*
    00190  * values for ibs_param_t.options
    00191  */
    00192 #define IBS_OPTIONS_RANDEN 1    /* enable randomization (IBS fetch only) */
    00193 #define IBS_OPTIONS_UOPS   1    /* count dispatched uops (IBS op only) */
    00194
    00195 typedef struct {
    00196         pfmlib_amd64_counter_t pfp_amd64_counters[PMU_AMD64_MAX_COUNTERS]; /* extended counter features */
    00197         uint32_t        flags;          /* use flags */
    00198         uint32_t        reserved1;      /* for future use */
    00199         ibs_param_t     ibsfetch;       /* IBS fetch control */
    00200         ibs_param_t     ibsop;          /* IBS execution control */
    00201         uint64_t        reserved2;      /* for future use */
    00202 } pfmlib_amd64_input_param_t;
    00203
    00204 /* A bit mask, meaning multiple usage types may be defined */
    00205 #define PFMLIB_AMD64_USE_IBSFETCH       1
    00206 #define PFMLIB_AMD64_USE_IBSOP          2
    00207
    00208 /*
    00209  * AMD64 specific output parameters for the library
    00210  *
    00211  * The values ibsfetch_base and ibsop_base pass back the index of the
    00212  * ibsopctl and ibsfetchctl register in pfp_pmds[].
    00213  */
    00214
    00215 typedef struct {
    00216         uint32_t        ibsfetch_base;  /* Perfmon2 base register index */
    00217         uint32_t        ibsop_base;     /* Perfmon2 base register index */
    00218         uint64_t        reserved[7];    /* for future use */
    00219 } pfmlib_amd64_output_param_t;
    00220
    00221 /* Perfmon2 registers relative to base register */
    00222 #define PMD_IBSFETCHCTL         0
    00223 #define PMD_IBSFETCHLINAD       1
    00224 #define PMD_IBSFETCHPHYSAD      2
    00225 #define PMD_IBSOPCTL            0
    00226 #define PMD_IBSOPRIP            1
    00227 #define PMD_IBSOPDATA           2
    00228 #define PMD_IBSOPDATA2          3
    00229 #define PMD_IBSOPDATA3          4
    00230 #define PMD_IBSDCLINAD          5
    00231 #define PMD_IBSDCPHYSAD         6
    00232
    00233 #ifdef __cplusplus /* extern C */
    00234 }
    00235 #endif
    00236
    00237 #endif /* __PFMLIB_AMD64_H__ */

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