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perfmon_pebs_core_smpl.h
Go to the documentation of this file.
1 /*
2 * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P.
3 * Contributed by Stephane Eranian <eranian@hpl.hp.com>
4 *
5 * This file implements the sampling format to support Intel
6 * Precise Event Based Sampling (PEBS) feature of Intel
7 * Core and Atom processors.
8 *
9 * What is PEBS?
10 * ------------
11 * This is a hardware feature to enhance sampling by providing
12 * better precision as to where a sample is taken. This avoids the
13 * typical skew in the instruction one can observe with any
14 * interrupt-based sampling technique.
15 *
16 * PEBS also lowers sampling overhead significantly by having the
17 * processor store samples instead of the OS. PMU interrupt are only
18 * generated after multiple samples are written.
19 *
20 * Another benefit of PEBS is that samples can be captured inside
21 * critical sections where interrupts are masked.
22 *
23 * How does it work?
24 * PEBS effectively implements a Hw buffer. The Os must pass a region
25 * of memory where samples are to be stored. The region can have any
26 * size. The OS must also specify the sampling period to reload. The PMU
27 * will interrupt when it reaches the end of the buffer or a specified
28 * threshold location inside the memory region.
29 *
30 * The description of the buffer is stored in the Data Save Area (DS).
31 * The samples are stored sequentially in the buffer. The format of the
32 * buffer is fixed and specified in the PEBS documentation. The sample
33 * format does not change between 32-bit and 64-bit modes unlike on the
34 * Pentium 4 version of PEBS.
35 *
36 * What does the format do?
37 * It provides access to the PEBS feature for both 32-bit and 64-bit
38 * processors that support it.
39 *
40 * The same code and data structures are used for both 32-bit and 64-bi
41 * modes. A single format name is used for both modes. In 32-bit mode,
42 * some of the extended registers are written to zero in each sample.
43 *
44 * It is important to realize that the format provides a zero-copy
45 * environment for the samples, i.e,, the OS never touches the
46 * samples. Whatever the processor write is directly accessible to
47 * the user.
48 *
49 * Parameters to the buffer can be passed via pfm_create_context() in
50 * the pfm_pebs_smpl_arg structure.
51 */
52 #ifndef __PERFMON_PEBS_CORE_SMPL_H__
53 #define __PERFMON_PEBS_CORE_SMPL_H__ 1
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 #include <perfmon/perfmon.h>
60
61 #define PFM_PEBS_CORE_SMPL_NAME "pebs_core"
62
63 /*
64 * format specific parameters (passed at context creation)
65 */
66 typedef struct {
67 uint64_t cnt_reset; /* counter reset value */
68 uint64_t buf_size; /* size of the buffer in bytes */
69 uint64_t intr_thres; /* index of interrupt threshold entry */
70 uint64_t reserved[6]; /* for future use */
71 } pfm_pebs_core_smpl_arg_t;
72
73 /*
74 * DS Save Area
75 */
76 typedef struct {
77 uint64_t bts_buf_base;
78 uint64_t bts_index;
79 uint64_t bts_abs_max;
80 uint64_t bts_intr_thres;
81 uint64_t pebs_buf_base;
82 uint64_t pebs_index;
83 uint64_t pebs_abs_max;
84 uint64_t pebs_intr_thres;
85 uint64_t pebs_cnt_reset;
86 } pfm_ds_area_core_t;
87
88 /*
89 * This header is at the beginning of the sampling buffer returned to the user.
90 *
91 * Because of PEBS alignement constraints, the actual PEBS buffer area does
92 * not necessarily begin right after the header. The hdr_start_offs must be
93 * used to compute the first byte of the buffer. The offset is defined as
94 * the number of bytes between the end of the header and the beginning of
95 * the buffer. As such the formula is:
96 * actual_buffer = (unsigned long)(hdr+1)+hdr->hdr_start_offs
97 */
98 typedef struct {
99 uint64_t overflows; /* #overflows for buffer */
100 size_t buf_size; /* bytes in the buffer */
101 size_t start_offs; /* actual buffer start offset */
102 uint32_t version; /* smpl format version */
103 uint32_t reserved1; /* for future use */
104 uint64_t reserved2[5]; /* for future use */
105 pfm_ds_area_core_t ds; /* DS management Area */
106 } pfm_pebs_core_smpl_hdr_t;
107
108 /*
109 * PEBS record format as for both 32-bit and 64-bit modes
110 */
111 typedef struct {
112 uint64_t eflags;
113 uint64_t ip;
114 uint64_t eax;
115 uint64_t ebx;
116 uint64_t ecx;
117 uint64_t edx;
118 uint64_t esi;
119 uint64_t edi;
120 uint64_t ebp;
121 uint64_t esp;
122 uint64_t r8; /* 0 in 32-bit mode */
123 uint64_t r9; /* 0 in 32-bit mode */
124 uint64_t r10; /* 0 in 32-bit mode */
125 uint64_t r11; /* 0 in 32-bit mode */
126 uint64_t r12; /* 0 in 32-bit mode */
127 uint64_t r13; /* 0 in 32-bit mode */
128 uint64_t r14; /* 0 in 32-bit mode */
129 uint64_t r15; /* 0 in 32-bit mode */
130 } pfm_pebs_core_smpl_entry_t;
131
132 #define PFM_PEBS_CORE_SMPL_VERSION_MAJ 1U
133 #define PFM_PEBS_CORE_SMPL_VERSION_MIN 0U
134 #define PFM_PEBS_CORE_SMPL_VERSION (((PFM_PEBS_CORE_SMPL_VERSION_MAJ&0xffff)<<16)|\
135 (PFM_PEBS_CORE_SMPL_VERSION_MIN & 0xffff))
136
137 #ifdef __cplusplus
138 };
139 #endif
140
141 #endif /* __PERFMON_PEBS_CORE_SMPL_H__ */
pfm_pebs_core_smpl_entry_t::ecx
uint64_t ecx
Definition: perfmon_pebs_core_smpl.h:116
pfm_pebs_core_smpl_entry_t::r13
uint64_t r13
Definition: perfmon_pebs_core_smpl.h:127
pfm_ds_area_core_t::pebs_buf_base
uint64_t pebs_buf_base
Definition: perfmon_pebs_core_smpl.h:81
pfm_pebs_core_smpl_entry_t::r15
uint64_t r15
Definition: perfmon_pebs_core_smpl.h:129
pfm_pebs_core_smpl_entry_t::ip
uint64_t ip
Definition: perfmon_pebs_core_smpl.h:113
pfm_pebs_core_smpl_entry_t::r11
uint64_t r11
Definition: perfmon_pebs_core_smpl.h:125
pfm_ds_area_core_t::pebs_index
uint64_t pebs_index
Definition: perfmon_pebs_core_smpl.h:82
pfm_pebs_core_smpl_entry_t::r8
uint64_t r8
Definition: perfmon_pebs_core_smpl.h:122
pfm_pebs_core_smpl_entry_t::esp
uint64_t esp
Definition: perfmon_pebs_core_smpl.h:121
pfm_ds_area_core_t::pebs_abs_max
uint64_t pebs_abs_max
Definition: perfmon_pebs_core_smpl.h:83
pfm_pebs_core_smpl_entry_t::edx
uint64_t edx
Definition: perfmon_pebs_core_smpl.h:117
pfm_pebs_core_smpl_hdr_t::version
uint32_t version
Definition: perfmon_pebs_core_smpl.h:102
uint64_t
unsigned long long uint64_t
Definition: instrset.h:144
pfm_pebs_core_smpl_arg_t::intr_thres
uint64_t intr_thres
Definition: perfmon_pebs_core_smpl.h:69
pfm_pebs_core_smpl_entry_t::esi
uint64_t esi
Definition: perfmon_pebs_core_smpl.h:118
pfm_ds_area_core_t
Definition: perfmon_pebs_core_smpl.h:76
pfm_pebs_core_smpl_hdr_t
Definition: perfmon_pebs_core_smpl.h:98
pfm_ds_area_core_t::bts_buf_base
uint64_t bts_buf_base
Definition: perfmon_pebs_core_smpl.h:77
pfm_ds_area_core_t::bts_intr_thres
uint64_t bts_intr_thres
Definition: perfmon_pebs_core_smpl.h:80
pfm_pebs_core_smpl_arg_t::buf_size
uint64_t buf_size
Definition: perfmon_pebs_core_smpl.h:68
pfm_pebs_core_smpl_entry_t::ebp
uint64_t ebp
Definition: perfmon_pebs_core_smpl.h:120
pfm_pebs_core_smpl_hdr_t::buf_size
size_t buf_size
Definition: perfmon_pebs_core_smpl.h:100
pfm_ds_area_core_t::bts_abs_max
uint64_t bts_abs_max
Definition: perfmon_pebs_core_smpl.h:79
pfm_ds_area_core_t::pebs_cnt_reset
uint64_t pebs_cnt_reset
Definition: perfmon_pebs_core_smpl.h:85
pfm_pebs_core_smpl_entry_t::r9
uint64_t r9
Definition: perfmon_pebs_core_smpl.h:123
pfm_pebs_core_smpl_entry_t::r14
uint64_t r14
Definition: perfmon_pebs_core_smpl.h:128
pfm_pebs_core_smpl_hdr_t::start_offs
size_t start_offs
Definition: perfmon_pebs_core_smpl.h:101
pfm_pebs_core_smpl_entry_t::ebx
uint64_t ebx
Definition: perfmon_pebs_core_smpl.h:115
pfm_pebs_core_smpl_entry_t::eflags
uint64_t eflags
Definition: perfmon_pebs_core_smpl.h:112
uint32_t
unsigned int uint32_t
Definition: instrset.h:142
pfm_pebs_core_smpl_arg_t::cnt_reset
uint64_t cnt_reset
Definition: perfmon_pebs_core_smpl.h:67
pfm_ds_area_core_t::pebs_intr_thres
uint64_t pebs_intr_thres
Definition: perfmon_pebs_core_smpl.h:84
pfm_pebs_core_smpl_hdr_t::overflows
uint64_t overflows
Definition: perfmon_pebs_core_smpl.h:99
pfm_ds_area_core_t::bts_index
uint64_t bts_index
Definition: perfmon_pebs_core_smpl.h:78
pfm_pebs_core_smpl_entry_t::edi
uint64_t edi
Definition: perfmon_pebs_core_smpl.h:119
pfm_pebs_core_smpl_entry_t::eax
uint64_t eax
Definition: perfmon_pebs_core_smpl.h:114
pfm_pebs_core_smpl_hdr_t::ds
pfm_ds_area_core_t ds
Definition: perfmon_pebs_core_smpl.h:105
pfm_pebs_core_smpl_entry_t
Definition: perfmon_pebs_core_smpl.h:111
perfmon.h
pfm_pebs_core_smpl_hdr_t::reserved1
uint32_t reserved1
Definition: perfmon_pebs_core_smpl.h:103
pfm_pebs_core_smpl_entry_t::r12
uint64_t r12
Definition: perfmon_pebs_core_smpl.h:126
pfm_pebs_core_smpl_arg_t
Definition: perfmon_pebs_core_smpl.h:66
pfm_pebs_core_smpl_entry_t::r10
uint64_t r10
Definition: perfmon_pebs_core_smpl.h:124