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perfmon_pebs_p4_smpl.h
Go to the documentation of this file.
1 /*
2 * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P.
3 * Contributed by Stephane Eranian <eranian@hpl.hp.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of version 2 of the GNU General Public
7 * License as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
17 * 02111-1307 USA
18 *
19 * This file implements the sampling format to support Intel
20 * Precise Event Based Sampling (PEBS) feature of Pentium 4
21 * and other Netburst-based processors. Not to be used for
22 * Intel Core-based processors.
23 *
24 * What is PEBS?
25 * ------------
26 * This is a hardware feature to enhance sampling by providing
27 * better precision as to where a sample is taken. This avoids the
28 * typical skew in the instruction one can observe with any
29 * interrupt-based sampling technique.
30 *
31 * PEBS also lowers sampling overhead significantly by having the
32 * processor store samples instead of the OS. PMU interrupt are only
33 * generated after multiple samples are written.
34 *
35 * Another benefit of PEBS is that samples can be captured inside
36 * critical sections where interrupts are masked.
37 *
38 * How does it work?
39 * PEBS effectively implements a Hw buffer. The Os must pass a region
40 * of memory where samples are to be stored. The region can have any
41 * size. The OS must also specify the sampling period to reload. The PMU
42 * will interrupt when it reaches the end of the buffer or a specified
43 * threshold location inside the memory region.
44 *
45 * The description of the buffer is stored in the Data Save Area (DS).
46 * The samples are stored sequentially in the buffer. The format of the
47 * buffer is fixed and specified in the PEBS documentation. The sample
48 * format changes between 32-bit and 64-bit modes due to extended register
49 * file.
50 *
51 * PEBS does not work when HyperThreading is enabled due to certain MSR
52 * being shared being to two threads.
53 *
54 * What does the format do?
55 * It provides access to the PEBS feature for both 32-bit and 64-bit
56 * processors that support it.
57 *
58 * The same code is used for both 32-bit and 64-bit modes, but different
59 * format names are used because the two modes are not compatible due to
60 * data model and register file differences. Similarly the public data
61 * structures describing the samples are different.
62 *
63 * It is important to realize that the format provides a zero-copy environment
64 * for the samples, i.e,, the OS never touches the samples. Whatever the
65 * processor write is directly accessible to the user.
66 *
67 * Parameters to the buffer can be passed via pfm_create_context() in
68 * the pfm_pebs_smpl_arg structure.
69 *
70 * It is not possible to mix a 32-bit PEBS application on top of a 64-bit
71 * host kernel.
72 */
73 #ifndef __PERFMON_PEBS_P4_SMPL_H__
74 #define __PERFMON_PEBS_P4_SMPL_H__ 1
75
76 #ifdef __cplusplus
77 extern "C" {
78 #endif
79
80 #include <perfmon/perfmon.h>
81
82 #ifdef __i386__
83 #define PFM_PEBS_P4_SMPL_NAME "pebs32_p4"
84 #else
85 #define PFM_PEBS_P4_SMPL_NAME "pebs64_p4"
86 #endif
87
88 /*
89 * format specific parameters (passed at context creation)
90 */
91 typedef struct {
92 uint64_t cnt_reset; /* counter reset value */
93 size_t buf_size; /* size of the buffer in bytes */
94 size_t intr_thres; /* index of interrupt threshold entry */
95 uint64_t reserved[6]; /* for future use */
96 } pfm_pebs_p4_smpl_arg_t;
97
98 /*
99 * DS Save Area as described in section 15.10.5
100 */
101 typedef struct {
102 unsigned long bts_buf_base;
103 unsigned long bts_index;
104 unsigned long bts_abs_max;
105 unsigned long bts_intr_thres;
106 unsigned long pebs_buf_base;
107 unsigned long pebs_index;
108 unsigned long pebs_abs_max;
109 unsigned long pebs_intr_thres;
110 uint64_t pebs_cnt_reset;
111 } pfm_ds_area_p4_t;
112
113 /*
114 * This header is at the beginning of the sampling buffer returned to the user.
115 *
116 * Because of PEBS alignement constraints, the actual PEBS buffer area does
117 * not necessarily begin right after the header. The hdr_start_offs must be
118 * used to compute the first byte of the buffer. The offset is defined as
119 * the number of bytes between the end of the header and the beginning of
120 * the buffer. As such the formula is:
121 * actual_buffer = (unsigned long)(hdr+1)+hdr->hdr_start_offs
122 */
123 typedef struct {
124 uint64_t overflows; /* #overflows for buffer */
125 size_t buf_size; /* bytes in the buffer */
126 size_t start_offs; /* actual buffer start offset */
127 uint32_t version; /* smpl format version */
128 uint32_t reserved1; /* for future use */
129 uint64_t reserved2[5]; /* for future use */
130 pfm_ds_area_p4_t ds; /* DS management Area */
131 } pfm_pebs_p4_smpl_hdr_t;
132
133 /*
134 * PEBS record format as for both 32-bit and 64-bit modes
135 */
136 typedef struct {
137 unsigned long eflags;
138 unsigned long ip;
139 unsigned long eax;
140 unsigned long ebx;
141 unsigned long ecx;
142 unsigned long edx;
143 unsigned long esi;
144 unsigned long edi;
145 unsigned long ebp;
146 unsigned long esp;
147 #ifdef __x86_64__
148 unsigned long r8;
149 unsigned long r9;
150 unsigned long r10;
151 unsigned long r11;
152 unsigned long r12;
153 unsigned long r13;
154 unsigned long r14;
155 unsigned long r15;
156 #endif
157 } pfm_pebs_p4_smpl_entry_t;
158
159 #define PFM_PEBS_P4_SMPL_VERSION_MAJ 1U
160 #define PFM_PEBS_P4_SMPL_VERSION_MIN 0U
161 #define PFM_PEBS_P4_SMPL_VERSION \
162 ( ( ( PFM_PEBS_P4_SMPL_VERSION_MAJ & 0xffff ) << 16 ) | ( PFM_PEBS_P4_SMPL_VERSION_MIN & 0xffff ) )
163
164 #ifdef __cplusplus
165 };
166 #endif
167
168 #endif /* __PERFMON_PEBS_P4_SMPL_H__ */
pfm_pebs_p4_smpl_hdr_t::start_offs
size_t start_offs
Definition: perfmon_pebs_p4_smpl.h:126
pfm_ds_area_p4_t::bts_abs_max
unsigned long bts_abs_max
Definition: perfmon_pebs_p4_smpl.h:104
pfm_ds_area_p4_t
Definition: perfmon_pebs_p4_smpl.h:101
pfm_ds_area_p4_t::bts_buf_base
unsigned long bts_buf_base
Definition: perfmon_pebs_p4_smpl.h:102
pfm_pebs_p4_smpl_entry_t::ebx
unsigned long ebx
Definition: perfmon_pebs_p4_smpl.h:140
pfm_pebs_p4_smpl_arg_t::buf_size
size_t buf_size
Definition: perfmon_pebs_p4_smpl.h:93
pfm_pebs_p4_smpl_hdr_t::buf_size
size_t buf_size
Definition: perfmon_pebs_p4_smpl.h:125
pfm_pebs_p4_smpl_entry_t::eax
unsigned long eax
Definition: perfmon_pebs_p4_smpl.h:139
pfm_pebs_p4_smpl_entry_t
Definition: perfmon_pebs_p4_smpl.h:136
uint64_t
unsigned long long uint64_t
Definition: instrset.h:143
pfm_ds_area_p4_t::pebs_cnt_reset
uint64_t pebs_cnt_reset
Definition: perfmon_pebs_p4_smpl.h:110
pfm_ds_area_p4_t::bts_intr_thres
unsigned long bts_intr_thres
Definition: perfmon_pebs_p4_smpl.h:105
pfm_pebs_p4_smpl_entry_t::eflags
unsigned long eflags
Definition: perfmon_pebs_p4_smpl.h:137
pfm_ds_area_p4_t::bts_index
unsigned long bts_index
Definition: perfmon_pebs_p4_smpl.h:103
pfm_pebs_p4_smpl_entry_t::edx
unsigned long edx
Definition: perfmon_pebs_p4_smpl.h:142
pfm_pebs_p4_smpl_hdr_t::reserved1
uint32_t reserved1
Definition: perfmon_pebs_p4_smpl.h:128
pfm_pebs_p4_smpl_hdr_t::version
uint32_t version
Definition: perfmon_pebs_p4_smpl.h:127
pfm_pebs_p4_smpl_arg_t
Definition: perfmon_pebs_p4_smpl.h:91
pfm_pebs_p4_smpl_entry_t::esi
unsigned long esi
Definition: perfmon_pebs_p4_smpl.h:143
pfm_pebs_p4_smpl_hdr_t::overflows
uint64_t overflows
Definition: perfmon_pebs_p4_smpl.h:124
pfm_ds_area_p4_t::pebs_intr_thres
unsigned long pebs_intr_thres
Definition: perfmon_pebs_p4_smpl.h:109
pfm_pebs_p4_smpl_entry_t::esp
unsigned long esp
Definition: perfmon_pebs_p4_smpl.h:146
pfm_pebs_p4_smpl_arg_t::intr_thres
size_t intr_thres
Definition: perfmon_pebs_p4_smpl.h:94
pfm_ds_area_p4_t::pebs_abs_max
unsigned long pebs_abs_max
Definition: perfmon_pebs_p4_smpl.h:108
pfm_ds_area_p4_t::pebs_buf_base
unsigned long pebs_buf_base
Definition: perfmon_pebs_p4_smpl.h:106
pfm_pebs_p4_smpl_arg_t::cnt_reset
uint64_t cnt_reset
Definition: perfmon_pebs_p4_smpl.h:92
uint32_t
unsigned int uint32_t
Definition: instrset.h:141
pfm_ds_area_p4_t::pebs_index
unsigned long pebs_index
Definition: perfmon_pebs_p4_smpl.h:107
pfm_pebs_p4_smpl_entry_t::ebp
unsigned long ebp
Definition: perfmon_pebs_p4_smpl.h:145
pfm_pebs_p4_smpl_hdr_t::ds
pfm_ds_area_p4_t ds
Definition: perfmon_pebs_p4_smpl.h:130
pfm_pebs_p4_smpl_entry_t::ip
unsigned long ip
Definition: perfmon_pebs_p4_smpl.h:138
pfm_pebs_p4_smpl_hdr_t
Definition: perfmon_pebs_p4_smpl.h:123
pfm_pebs_p4_smpl_entry_t::ecx
unsigned long ecx
Definition: perfmon_pebs_p4_smpl.h:141
perfmon.h
pfm_pebs_p4_smpl_entry_t::edi
unsigned long edi
Definition: perfmon_pebs_p4_smpl.h:144