13 A test modeling a cycle in the DF realm.
17 from Configurables
import HiveWhiteBoard, HiveSlimEventLoopMgr, AvalancheSchedulerSvc, CPUCruncher, CPUCrunchSvc, PrecedenceSvc
24 CPUCrunchSvc(shortCalib=
True)
26 PrecedenceSvc(OutputLevel=DEBUG)
28 whiteboard = HiveWhiteBoard(
29 "EventDataSvc", EventSlots=evtslots, OutputLevel=INFO)
31 slimeventloopmgr = HiveSlimEventLoopMgr(
32 SchedulerName=
"AvalancheSchedulerSvc", OutputLevel=INFO)
34 AvalancheSchedulerSvc(ThreadPoolSize=algosInFlight)
37 Alg1 = CPUCruncher(name=
"CycledAlg1")
38 Alg1.inpKeys = [
"/Event/B",
"/Event/F"]
39 Alg1.outKeys = [
"/Event/C",
"/Event/A"]
41 Alg2 = CPUCruncher(name=
"CycledAlg2")
42 Alg2.inpKeys = [
"/Event/C"]
43 Alg2.outKeys = [
"/Event/D",
"/Event/B"]
45 Alg3 = CPUCruncher(name=
"CycledAlg3")
46 Alg3.inpKeys = [
"/Event/D"]
47 Alg3.outKeys = [
"/Event/F"]
50 Alg4 = CPUCruncher(name=
"Alg4")
51 Alg4.inpKeys = [
"/Event/A"]
53 Alg5 = CPUCruncher(name=
"Alg5")
54 Alg5.outKeys = [
"/Event/E"]
60 EventLoop=slimeventloopmgr,
61 TopAlg=[Alg1, Alg2, Alg3, Alg4, Alg5],
62 MessageSvcType=
"InertMessageSvc",