pfmlib_pentium4.h

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00001 /*
00002  * Intel Pentium 4 PMU specific types and definitions (32 and 64 bit modes)
00003  *
00004  * Copyright (c) 2006 IBM Corp.
00005  * Contributed by Kevin Corry <kevcorry@us.ibm.com>
00006  *
00007  * Permission is hereby granted, free of charge, to any person obtaining a copy
00008  * of this software and associated documentation files (the "Software"), to deal
00009  * in the Software without restriction, including without limitation the rights
00010  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
00011  * of the Software, and to permit persons to whom the Software is furnished to do so,
00012  * subject to the following conditions:
00013  *
00014  * The above copyright notice and this permission notice shall be included in all
00015  * copies or substantial portions of the Software.
00016  *
00017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
00018  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
00019  * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
00020  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
00021  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
00022  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00023  */
00024 
00025 #ifndef __PFMLIB_PENTIUM4_H__
00026 #define __PFMLIB_PENTIUM4_H__
00027 
00028 #include <perfmon/pfmlib.h>
00029 
00030 /* ESCR: Event Selection Control Register
00031  *
00032  * These registers are used to select which event to count along with options
00033  * for that event. There are (up to) 45 ESCRs, but each data counter is
00034  * restricted to a specific set of ESCRs.
00035  */
00036 
00055 #define EVENT_MASK_BITS 16
00056 #define EVENT_SELECT_BITS 6
00057 
00058 typedef union {
00059         unsigned long val;
00060         struct {
00061                 unsigned long t1_usr:1;
00062                 unsigned long t1_os:1;
00063                 unsigned long t0_usr:1;
00064                 unsigned long t0_os:1;
00065                 unsigned long tag_enable:1;
00066                 unsigned long tag_value:4;
00067                 unsigned long event_mask:EVENT_MASK_BITS;
00068                 unsigned long event_select:EVENT_SELECT_BITS;
00069                 unsigned long reserved:1;
00070         } bits;
00071 } pentium4_escr_value_t;
00072 
00073 /* CCCR: Counter Configuration Control Register
00074  *
00075  * These registers are used to configure the data counters. There are 18
00076  * CCCRs, one for each data counter.
00077  */
00078 
00111 typedef union {
00112         unsigned long val;
00113         struct {
00114                 unsigned long reserved1:12;
00115                 unsigned long enable:1;
00116                 unsigned long escr_select:3;
00117                 unsigned long active_thread:2;
00118                 unsigned long compare:1;
00119                 unsigned long complement:1;
00120                 unsigned long threshold:4;
00121                 unsigned long edge:1;
00122                 unsigned long force_ovf:1;
00123                 unsigned long ovf_pmi_t0:1;
00124                 unsigned long ovf_pmi_t1:1;
00125                 unsigned long reserved2:2;
00126                 unsigned long cascade:1;
00127                 unsigned long overflow:1;
00128         } bits;
00129 } pentium4_cccr_value_t;
00130 
00131 #endif /* __PFMLIB_PENTIUM4_H__ */
Gaudi Framework, version v22r0

pfmlib_pentium4.h
