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pfmlib_amd64.h
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1 /*
2  * AMD64 PMU specific types and definitions (64 and 32 bit modes)
3  *
4  * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P.
5  * Contributed by Stephane Eranian <eranian@hpl.hp.com>
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
11  * of the Software, and to permit persons to whom the Software is furnished to do so,
12  * subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in all
15  * copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
18  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
19  * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
20  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
21  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
22  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef __PFMLIB_AMD64_H__
26 #define __PFMLIB_AMD64_H__
27 
28 #include <stdint.h>
29 
30 /*
31  * privilege level mask usage for AMD64:
32  *
33  * PFM_PLM0 = OS (kernel, hypervisor, ..)
34  * PFM_PLM1 = invalid parameters
35  * PFM_PLM2 = invalid parameters
36  * PFM_PLM3 = USR (user level)
37  */
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
43 #define PMU_AMD64_MAX_COUNTERS 4 /* total numbers of performance counters */
44 
45 /*
46  * AMD64 MSR definitions
47  */
48 
49 typedef union {
50  uint64_t val; /* complete register value */
51  struct {
52  uint64_t sel_event_mask:8; /* event mask */
53  uint64_t sel_unit_mask:8; /* unit mask */
54  uint64_t sel_usr:1; /* user level */
55  uint64_t sel_os:1; /* system level */
56  uint64_t sel_edge:1; /* edge detec */
57  uint64_t sel_pc:1; /* pin control */
58  uint64_t sel_int:1; /* enable APIC intr */
59  uint64_t sel_res1:1; /* reserved */
60  uint64_t sel_en:1; /* enable */
61  uint64_t sel_inv:1; /* invert counter mask */
62  uint64_t sel_cnt_mask:8; /* counter mask */
63  uint64_t sel_event_mask2:4; /* 10h only: event mask [11:8] */
64  uint64_t sel_res2:4; /* reserved */
65  uint64_t sel_guest:1; /* 10h only: guest only counter */
66  uint64_t sel_host:1; /* 10h only: host only counter */
67  uint64_t sel_res3:22; /* reserved */
68  } perfsel;
69 } pfm_amd64_sel_reg_t; /* MSR 0xc001000-0xc001003 */
70 
71 typedef union {
72  uint64_t val; /* complete register value */
73  struct {
74  uint64_t ctr_count:48; /* 48-bit hardware counter */
75  uint64_t ctr_res1:16; /* reserved */
76  } perfctr;
77 } pfm_amd64_ctr_reg_t; /* MSR 0xc001004-0xc001007 */
78 
79 typedef union {
80  uint64_t val; /* complete register value */
81  struct {
82  uint64_t ibsfetchmaxcnt:16;
83  uint64_t ibsfetchcnt:16;
84  uint64_t ibsfetchlat:16;
85  uint64_t ibsfetchen:1;
86  uint64_t ibsfetchval:1;
87  uint64_t ibsfetchcomp:1;
88  uint64_t ibsicmiss:1;
89  uint64_t ibsphyaddrvalid:1;
90  uint64_t ibsl1tlbpgsz:2;
91  uint64_t ibsl1tlbmiss:1;
92  uint64_t ibsl2tlbmiss:1;
93  uint64_t ibsranden:1;
94  uint64_t reserved:6;
95  } reg;
96 } ibsfetchctl_t; /* MSR 0xc0011030 */
97 
98 typedef union {
99  uint64_t val; /* complete register value */
100  struct {
101  uint64_t ibsopmaxcnt:16;
102  uint64_t reserved1:1;
103  uint64_t ibsopen:1;
104  uint64_t ibsopval:1;
105  uint64_t ibsopcntl:1;
106  uint64_t reserved2:44;
107  } reg;
108 } ibsopctl_t; /* MSR 0xc0011033 */
109 
110 typedef union {
111  uint64_t val; /* complete register value */
112  struct {
113  uint64_t ibscomptoretctr:16;
114  uint64_t ibstagtoretctr:16;
115  uint64_t ibsopbrnresync:1;
116  uint64_t ibsopmispreturn:1;
117  uint64_t ibsopreturn:1;
118  uint64_t ibsopbrntaken:1;
119  uint64_t ibsopbrnmisp:1;
120  uint64_t ibsopbrnret:1;
121  uint64_t reserved:26;
122  } reg;
123 } ibsopdata_t; /* MSR 0xc0011035 */
124 
125 typedef union {
126  uint64_t val; /* complete register value */
127  struct {
128  uint64_t nbibsreqsrc:3;
129  uint64_t reserved1:1;
130  uint64_t nbibsreqdstproc:1;
131  uint64_t nbibsreqcachehitst:1;
132  uint64_t reserved2:58;
133  } reg;
134 } ibsopdata2_t; /* MSR 0xc0011036 */
135 
136 typedef union {
137  uint64_t val; /* complete register value */
138  struct {
139  uint64_t ibsldop:1;
140  uint64_t ibsstop:1;
141  uint64_t ibsdcl1tlbmiss:1;
142  uint64_t ibsdcl2tlbmiss:1;
143  uint64_t ibsdcl1tlbhit2m:1;
144  uint64_t ibsdcl1tlbhit1g:1;
145  uint64_t ibsdcl2tlbhit2m:1;
146  uint64_t ibsdcmiss:1;
147  uint64_t ibsdcmissacc:1;
148  uint64_t ibsdcldbnkcon:1;
149  uint64_t ibsdcstbnkcon:1;
150  uint64_t ibsdcsttoldfwd:1;
151  uint64_t ibsdcsttoldcan:1;
152  uint64_t ibsdcucmemacc:1;
153  uint64_t ibsdcwcmemacc:1;
154  uint64_t ibsdclockedop:1;
155  uint64_t ibsdcmabhit:1;
156  uint64_t ibsdclinaddrvalid:1;
157  uint64_t ibsdcphyaddrvalid:1;
158  uint64_t reserved1:13;
159  uint64_t ibsdcmisslat:16;
160  uint64_t reserved2:16;
161  } reg;
162 } ibsopdata3_t; /* MSR 0xc0011037 */
163 
164 /*
165  * AMD64 specific input parameters for the library
166  */
167 
168 typedef struct {
169  uint32_t cnt_mask; /* threshold ([4-255] are reserved) */
170  uint32_t flags; /* counter specific flag */
171 } pfmlib_amd64_counter_t;
172 
173 #define PFM_AMD64_SEL_INV 0x1 /* inverse */
174 #define PFM_AMD64_SEL_EDGE 0x2 /* edge detect */
175 #define PFM_AMD64_SEL_GUEST 0x4 /* guest only */
176 #define PFM_AMD64_SEL_HOST 0x8 /* host only */
177 
178 /*
179  * IBS input parameters
180  *
181  * Maxcnt specifies the maximum count value of the periodic counter,
182  * 20 bits, bits 3:0 are always set to zero.
183  */
184 typedef struct {
185  unsigned int maxcnt;
186  unsigned int options;
187 } ibs_param_t;
188 
189 /*
190  * values for ibs_param_t.options
191  */
192 #define IBS_OPTIONS_RANDEN 1 /* enable randomization (IBS fetch only) */
193 #define IBS_OPTIONS_UOPS 1 /* count dispatched uops (IBS op only) */
194 
195 typedef struct {
196  pfmlib_amd64_counter_t pfp_amd64_counters[PMU_AMD64_MAX_COUNTERS]; /* extended counter features */
197  uint32_t flags; /* use flags */
198  uint32_t reserved1; /* for future use */
199  ibs_param_t ibsfetch; /* IBS fetch control */
200  ibs_param_t ibsop; /* IBS execution control */
201  uint64_t reserved2; /* for future use */
202 } pfmlib_amd64_input_param_t;
203 
204 /* A bit mask, meaning multiple usage types may be defined */
205 #define PFMLIB_AMD64_USE_IBSFETCH 1
206 #define PFMLIB_AMD64_USE_IBSOP 2
207 
208 /*
209  * AMD64 specific output parameters for the library
210  *
211  * The values ibsfetch_base and ibsop_base pass back the index of the
212  * ibsopctl and ibsfetchctl register in pfp_pmds[].
213  */
214 
215 typedef struct {
216  uint32_t ibsfetch_base; /* Perfmon2 base register index */
217  uint32_t ibsop_base; /* Perfmon2 base register index */
218  uint64_t reserved[7]; /* for future use */
219 } pfmlib_amd64_output_param_t;
220 
221 /* Perfmon2 registers relative to base register */
222 #define PMD_IBSFETCHCTL 0
223 #define PMD_IBSFETCHLINAD 1
224 #define PMD_IBSFETCHPHYSAD 2
225 #define PMD_IBSOPCTL 0
226 #define PMD_IBSOPRIP 1
227 #define PMD_IBSOPDATA 2
228 #define PMD_IBSOPDATA2 3
229 #define PMD_IBSOPDATA3 4
230 #define PMD_IBSDCLINAD 5
231 #define PMD_IBSDCPHYSAD 6
232 
233 #ifdef __cplusplus /* extern C */
234 }
235 #endif
236 
237 #endif /* __PFMLIB_AMD64_H__ */