13 A test modeling a cycle in the DF realm.
16 from Configurables
import (
17 AvalancheSchedulerSvc,
31 CPUCrunchSvc(shortCalib=
True)
33 PrecedenceSvc(OutputLevel=DEBUG)
35 whiteboard = HiveWhiteBoard(
"EventDataSvc", EventSlots=evtslots, OutputLevel=INFO)
37 slimeventloopmgr = HiveSlimEventLoopMgr(
38 SchedulerName=
"AvalancheSchedulerSvc", OutputLevel=INFO
41 AvalancheSchedulerSvc(ThreadPoolSize=algosInFlight)
44 Alg1 = CPUCruncher(name=
"CycledAlg1")
45 Alg1.inpKeys = [
"/Event/B",
"/Event/F"]
46 Alg1.outKeys = [
"/Event/C",
"/Event/A"]
48 Alg2 = CPUCruncher(name=
"CycledAlg2")
49 Alg2.inpKeys = [
"/Event/C"]
50 Alg2.outKeys = [
"/Event/D",
"/Event/B"]
52 Alg3 = CPUCruncher(name=
"CycledAlg3")
53 Alg3.inpKeys = [
"/Event/D"]
54 Alg3.outKeys = [
"/Event/F"]
57 Alg4 = CPUCruncher(name=
"Alg4")
58 Alg4.inpKeys = [
"/Event/A"]
60 Alg5 = CPUCruncher(name=
"Alg5")
61 Alg5.outKeys = [
"/Event/E"]
67 EventLoop=slimeventloopmgr,
68 TopAlg=[Alg1, Alg2, Alg3, Alg4, Alg5],
69 MessageSvcType=
"InertMessageSvc",