#include <pfmlib_pentium4.h>

Public Attributes
unsigned long	val
struct {
unsigned long reserved1:12
unsigned long enable:1
unsigned long escr_select:3
unsigned long active_thread:2
unsigned long compare:1
unsigned long complement:1
unsigned long threshold:4
unsigned long edge:1
unsigned long force_ovf:1
unsigned long ovf_pmi_t0:1
unsigned long ovf_pmi_t1:1
unsigned long reserved2:2
unsigned long cascade:1
unsigned long overflow:1
}	bits

Detailed Description

pentium4_cccr_value_t

Bit-wise breakdown of the CCCR registers.

Bits Description ------- ----------- 63 - 32 Reserved 31 OVF - The data counter overflowed. 30 Cascade - Enable cascading of data counter when alternate counter overflows. 29 - 28 Reserved 27 OVF_PMI_T1 - Generate interrupt for LP1 on counter overflow 26 OVF_PMI_T0 - Generate interrupt for LP0 on counter overflow 25 FORCE_OVF - Force interrupt on every counter increment 24 Edge - Enable rising edge detection of the threshold comparison output for filtering event counts. 23 - 20 Threshold Value - Select the threshold value for comparing to incoming event counts. 19 Complement - Select how incoming event count is compared with the threshold value. 18 Compare - Enable filtering of event counts. 17 - 16 Active Thread - Only used with HT enabled. 00 - None: Count when neither LP is active. 01 - Single: Count when only one LP is active. 10 - Both: Count when both LPs are active. 11 - Any: Count when either LP is active. 15 - 13 ESCR Select - Select which ESCR to use for selecting the event to count. 12 Enable - Turns the data counter on or off. 11 - 0 Reserved

Definition at line 111 of file pfmlib_pentium4.h.