The Gaudi Framework  v30r3 (a5ef0a68)
pfmlib_pentium4.h
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1 /*
2  * Intel Pentium 4 PMU specific types and definitions (32 and 64 bit modes)
3  *
4  * Copyright (c) 2006 IBM Corp.
5  * Contributed by Kevin Corry <kevcorry@us.ibm.com>
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
11  * of the Software, and to permit persons to whom the Software is furnished to do so,
12  * subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in all
15  * copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
18  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
19  * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
20  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
21  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
22  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef __PFMLIB_PENTIUM4_H__
26 #define __PFMLIB_PENTIUM4_H__
27 
28 #include <perfmon/pfmlib.h>
29 
30 /* ESCR: Event Selection Control Register
31  *
32  * These registers are used to select which event to count along with options
33  * for that event. There are (up to) 45 ESCRs, but each data counter is
34  * restricted to a specific set of ESCRs.
35  */
36 
55 #define EVENT_MASK_BITS 16
56 #define EVENT_SELECT_BITS 6
57 
58 typedef union {
59  unsigned long val;
60  struct {
61  unsigned long t1_usr : 1;
62  unsigned long t1_os : 1;
63  unsigned long t0_usr : 1;
64  unsigned long t0_os : 1;
65  unsigned long tag_enable : 1;
66  unsigned long tag_value : 4;
67  unsigned long event_mask : EVENT_MASK_BITS;
68  unsigned long event_select : EVENT_SELECT_BITS;
69  unsigned long reserved : 1;
70  } bits;
71 } pentium4_escr_value_t;
72 
73 /* CCCR: Counter Configuration Control Register
74  *
75  * These registers are used to configure the data counters. There are 18
76  * CCCRs, one for each data counter.
77  */
78 
111 typedef union {
112  unsigned long val;
113  struct {
114  unsigned long reserved1 : 12;
115  unsigned long enable : 1;
116  unsigned long escr_select : 3;
117  unsigned long active_thread : 2;
118  unsigned long compare : 1;
119  unsigned long complement : 1;
120  unsigned long threshold : 4;
121  unsigned long edge : 1;
122  unsigned long force_ovf : 1;
123  unsigned long ovf_pmi_t0 : 1;
124  unsigned long ovf_pmi_t1 : 1;
125  unsigned long reserved2 : 2;
126  unsigned long cascade : 1;
127  unsigned long overflow : 1;
128  } bits;
129 } pentium4_cccr_value_t;
130 
131 #endif /* __PFMLIB_PENTIUM4_H__ */
EVENT_SELECT_BITS
#define EVENT_SELECT_BITS
Definition: pfmlib_pentium4.h:56
pentium4_cccr_value_t
pentium4_cccr_value_t
Definition: pfmlib_pentium4.h:111
pentium4_escr_value_t::val
unsigned long val
Definition: pfmlib_pentium4.h:59
pentium4_escr_value_t
Definition: pfmlib_pentium4.h:58
pentium4_cccr_value_t::val
unsigned long val
Definition: pfmlib_pentium4.h:112
EVENT_MASK_BITS
#define EVENT_MASK_BITS
pentium4_escr_value_t
Definition: pfmlib_pentium4.h:55